DIGITAL LOGIC DESIGN (ECE_271_001_F2019)

DIGITAL LOGIC DESIGN (ECE_271_001_F2019)

Matthew's Office Hours in KEC 1115:

Monday 11 AM - 1 PM

Tuesday 10 AM - Noon

 

GTA Office Hours in KEC Atrium:

Emanuel (Primarily Lab Software): Tuesday 4 to 6pm
Joshua (Primarily Reading Reports): Thursday 4 to 6pm
Jialin (Primarily Weekly Quizzes): Friday 3 to 5pm

 

Course Syllabus:

Course Textbook:  Digital Design and Computer Architecture, David Money Harris & Sarah Harris

Lab Website:

TA Labs and Office Hours, in Dearborn 203:

 

Chapter 1 Reading Report (Graded as 85%, a B paper):

Chapter 1 Example Problems:

Chapter 1 Reading Report (LaTex Files):

 

Chapter 4 HDL Examples (zip):

Chapter 4 HDL Example (pdf): 

Video Introduction to ModelSim

ModelSim Manual 

ModelSim Command Reference

 

Textbook Slides

Chapter 1

Chapter 2

Chapter 3

Chapter 4

Chapter 5

Chapter 6 (not used in ECE 271)

Chapter 7 (not used in ECE 271)

Chapter 8 (not used in ECE 271)

Answers to textbook questions (mostly correct)

 

Mr. Shuman's Extra 271 Notes

Note Source Files (LaTex)

 

Course Summary:

Date Details