DIGITAL LOGIC DESIGN (ECE_271_001_S2020)

DIGITAL LOGIC DESIGN (ECE_271_001_S2020)

Special Spring 2020 Links

 

Contact Information

Matthew's Office Hours in Spring 2020:

Held Via Zoom

Monday 2 PM - 4 PM

Tuesday 1 PM - 3 PM

 

GTA Office Hours by appointment:

Emanuel Caceres cacereem@oregonstate.edu
Dilan Senaratne   senaratg@oregonstate.edu
Tzu-Hsuan Chou   choutz@oregonstate.edu

 

Course Syllabus:

 

Recorded Lectures:

I will get better at these online lectures.  There were some significant problems with using Zoom and making the recording for this first video.  The next lectures will be better.  Thank you for your patience.

Week 1:  Monday 1 2      Wednesday 1  2  3       Friday 1 2 3 Notes

Week 2:  Monday 1 2 3   Wednesday                    Friday

Week 3:  Monday  Wednesday   Friday

Week 4:  Monday  Wednesday  Friday

Week 5:  Monday  Wednesday  Friday

Week 6:  Monday  Wednesday  Friday

Week 7:  Monday  Wednesday  Friday

Week 8:  Monday  Wednesday  Friday

Week 9:  Monday  Wednesday Friday  SpriteDemo

Week A:  Monday  Wednesday  Friday

Final Exam:  Link

 

Textbook Resources:

Course Textbook:  Digital Design and Computer Architecture, David Money Harris & Sarah Harris

Chapter 1 Reading Report (Graded as 85%, a B paper):

Chapter 1 Example Problems:

Chapter 1 Reading Report (LaTex Files):

Chapter 1

Chapter 2

Chapter 3

Chapter 4

Chapter 5

Chapter 6 (not used in ECE 271)

Chapter 7 (not used in ECE 271)

Chapter 8 (not used in ECE 271)

Answers to textbook questions (mostly correct)

Mr. Shuman's Extra 271 Notes

Note Source Files (LaTex)

 

 

Lab Resources:

Lab Website:

TA Labs and Office Hours, over Zoom

 

System Verilog Resources:

Chapter 4 HDL Examples (zip):

Chapter 4 HDL Example (pdf): 

Video Introduction to ModelSim

ModelSim Manual 

ModelSim Command Reference

Course Summary:

Date Details